1. Field of the Invention
The present invention relates to a semiconductor memory device with a burst access mode capable of high speed readout, which can be used in devices such as memory cards.
2. Background Art
Recently, advances in processor technology have increased the degree of integration of semiconductor memory devices as well as the operating speed. The increase in the operating speeds of CPUs (central processing units) has been particularly marked. As a result, it is necessary to be able to read program data stored in semiconductor memory devices at high speeds corresponding with the operating speed of the CPU, and so an increase in the operating speed of semiconductor memory devices during readout has been required.
In particular, it is now possible to store musical information or graphical information such as animation on a single semiconductor chip, and then playback the musical information through speakers, or playback the graphical information on a display screen of a display device. If there is a variation in the read speed during read processing of the musical information or graphical information, then the music or graphics being played back may be interrupted and become non-continuous, causing a sense of incongruity for the user.
Consequently, for the readout of this type of musical information or graphical information, both a high speed, and a constant read speed are required.
The demand for high speed access of the aforementioned semiconductor memory devices, has seen the application of burst mode to the operation of such semiconductor memory devices. In burst mode for example, during the burst readout of data, when a reference address is provided to the semiconductor memory device, the data corresponding to the page is read to a latch at a time, and then based on a read enable signal at the semiconductor memory device, the necessary addresses for subsequent burst read processing from the aforementioned latch are generated sequentially within an internal circuit, thereby reading the data within the latch. Consequently, there is no necessity to read in the addresses anew, and so the access during memory readout occurs at high speed.
For example, as shown in FIG. 13, the data from the 16 bytes of memory cells between byte 0xcx9cbyte 15 is read during a latency period, and then while this data from byte 0xcx9cbyte 15 is being output, the data from the 16 bytes of memory cells between byte 16xcx9cbyte 31 is read. This read processing then repeats sequentially.
However, in the burst mode described above, on the completion of the readout of each page, the address of the next page is provided anew to the semiconductor memory device. As a result, the time taken for decode processing of the input address, that is, the time for page readout from the memory cells by the sense amplifier, is required, and a signal is retained for external control of the semiconductor memory device. In particular, as shown in FIG. 14, in the case of readout from a point partway through the 16 bytes, such as from the 15th byte, there is only the read time for a single byte in which to read from the memory cells all the data for byte 16xcx9cbyte 31, and so continuous data output is not achievable.
Consequently, in the method described above wherein a single page of data of a semiconductor memory device is latched, there is a practical limit to improvements in access time for high speed access. As a result, systems which utilize this type of semiconductor memory device suffer from the drawback that the processing speed of the entire system cannot be improved.
In order to resolve the above drawback, a sense amplifier and latch may be provided for every bit line used for memory data readout, so as to remove the requirement for a new address to be input every time the page is switched (Japanese Patent Application, First Publication No. Hei-9-106689).
As a result, because the data from all bit lines is read at a time and then stored in the respective latches, then with the exception of a change in the word line, high speed reading and writing can be carried out without the input of a new address. Consequently, systems which utilize this type of semiconductor memory device do not require a page read time on page switching, and so the overall processing speed can be improved.
However, in the above type of semiconductor memory device, because every bit line has a corresponding sense amplifier and a latch for storing the data from the sense amplifier, although access can be conducted at high speed, the area of the chip occupied by the sense amplifiers and latches is extremely large, and so in comparison with a normal semiconductor memory device of the same capacity, the chip surface area will be very large.
Furthermore, in the above type of semiconductor memory device, because every bit line has a corresponding sense amplifier and a latch for storing the data from the sense amplifier, the electric power consumption during operations such as data readout is extremely high, and so when used in battery driven portable information apparatus, the operating time of the portable information apparatus will be significantly shortened.
As a method of solving the aforementioned drawbacks of semiconductor memory devices, a read ciucuit construction which reduces the number of sense amplifiers has been proposed (Japanese Patent Application, First Publication No. Hei-11-176185), wherein the memory cell array is divided into a plurality of blocks, and a single sense amplifier is shared across the plurality of columns within each block. In such a case, in the plurality of blocks, the data of the selected columns is treated as a single set of data.
However, in the read circuit described above, when the first set of data is transferred from the sense amplifier to the shift register, an increment is added to the column address, and the second set of data is read to the sense amplifier. Then, when the last piece of data of the first set of data transferred to the shift register has been output, the second set of data is transferred into the shift register of the read circuit, another increment is added to the column address, and processing is carried out to read the third set of data into the sense amplifiers.
Consequently, the read circuit begins data output from the shift register after a predetermined random access time (for example, 1 xcexcsec) has passed. As a result, the read circuit is not equipped with a device for detecting, at the time when the output of the first set of data has been completed, whether or not evaluation of the second set of data by the sense amplifier has been completed.
Consequently, in those cases where the random access time of an external circuit or circuit device is, short relative to the access time of the semiconductor memory device, then at the point where the output of the first set of data is completed, the external circuit or circuit device will begin reading, assuming that the second set of data is being output from the shift register, even though the reading of that second set of data to the shift register is still incomplete, and consequently there is a danger that inaccurate reading of the data will occur.
Furthermore, because when the first set of data is transferred from the sense amplifier to the shift register, the read circuit adds an increment to the column address and begins readout of the second set of data to the sense amplifier, the sense amplifier is continually in an active state. Consequently, the read circuit suffers from large current consumption, as a current is continually flowing through the sense amplifier.
The present invention has been developed with consideration of these background circumstances, with an object of providing a semiconductor memory device which is capable of improving burst mode access time with no increase in chip surface area, and no increase in power consumption.
A first aspect of the present invention is a semiconductor memory device comprising a memory cell array with a plurality of arranged memory cells which are selected by a column address and a row address; a bit line selection circuit for selecting, based on the column address, a group comprising a predetermined number of bit lines, from bit lines connected with the plurality of memory cells selected by the row address; a sense amplifier section comprising sense amplifiers for determining for each bit line output signals from memory cells input through the plurality of bit lines of the selected group, and outputting data from each of the bit lines as an evaluation result; a first latch group and a second latch group connected in common to the sense amplifier section, for storing the data of each bit line output from the sense amplifier section; and a latch selection circuit for selecting which of the first latch group data and the second latch group data to output, and then outputting a selection result as read data; wherein during burst read operation, in cases where data of the first latch group is being output as read data, the second latch group stores data from the sense amplifier, and in cases where data of the second latch group is being output as read data, the first latch group stores data from the sense amplifier.
A second aspect of the present invention is a semiconductor memory device according to the first aspect, wherein the first latch group and the second latch group latch continuous data during a latency period.
A third aspect of the present invention is a semiconductor memory device according to either one of the first aspect and the second aspect, further equipped with a sense amplifier control device, wherein when data is being stored from the sense amplifier into either one of the first latch group and the second latch group, the sense amplifier is set to an active state, and when data has been stored in either one of the first latch group and the second latch group, the sense amplifier is set to a non-active state.
A fourth aspect of the present invention is a semiconductor memory device according to any one of the first aspect through the third aspect, further comprising a detection signal generation circuit for detecting, during latching of continuous data to the first latch group and the second latch group during a latency period, when latching of data from both the first latch group and the second latch group has been completed, and outputting a detection signal.
A fifth aspect of the present invention is a semiconductor memory device according to any one of the first aspect though the fourth aspect, farther comprising a counter for setting an input address as an initial value for a burst read column address, and counting from the set initial value each time a read signal is input, and generating a burst address.
A sixth aspect of the present invention is a semiconductor memory device according to the fifth aspect, wherein the counter comprises a first counter for generating a burst address for selecting which of the read data output from the first latch and the second latch will be output from an output terminal, and a second counter for generating a burst address which functions as a selection signal for selecting, from bit lines connected to selected memory cells, those bit lines of the group for connection to a sense amplifier.
A seventh aspect of the present invention is a semiconductor memory device according to the fifth aspect, wherein the counter comprises a first counter for generating a burst address for selecting which of the read data output from the first latch and the second latch will be output from an output terminal, a second counter for generating a burst address which functions as a selection signal for selecting, from bit lines connected to selected memory cells, those bit lines of the group for connection to a sense amplifier, and a third counter for generating a burst address which functions as a column address.
An eighth aspect of the present invention is a method of reading data from a semiconductor memory device comprising a first step for selecting from a memory array with a plurality of arranged memory cells which are selected by a column address and a row address, a plurality of the memory cells based on the row address; a second step in which a bit line selection circuit selects a group comprising a predetermined number of bit lines based on the column address, from bit lines connected with selected the plurality of memory cells; a third step in which a sense amplifier section for determining output signals from memory cells, input via the plurality of bit lines of the selected group, using a sense amplifier corresponding with each bit line, and outputs data from each of the bit lines as an evaluation result; a fourth step in which either one of a first latch and a second latch connected in common to the sense amplifier section stores the data of each bit line output from the sense amplifier section; and a fifth step in which a latch selection circuit selects which of the first latch data and the second latch data to output, and then outputs selected latch data as read data; wherein during burst read operation, in cases where data of the first latch is being output as read data, the second latch stores data from the sense amplifier, and in cases where data of the second latch is being output as read data, the first latch stores data from the sense amplifier.
A ninth aspect of the present invention is a method of reading data from a semiconductor memory device according to the eighth aspect, wherein the first latch group and the second latch group latch continuous data during a latency period
A tenth aspect of the present invention is a method of reading data from a semiconductor memory device according to either one of the eighth aspect and the ninth aspect, further comprising a sense amplifier control device, wherein when data is being stored from the sense amplifier into either one of the first latch group and the second latch group, the sense amplifier is set to an active state, and when data has been stored in either one of the first latch group and the second latch group, the sense amplifier is set to a non-active state.
An eleventh aspect of the present invention is a method of reading data from a semiconductor memory device according to any one of the eighth aspect through the tenth aspect, further comprising a detection signal generation circuit for detecting, during latching of continuous data to the first latch group and the second latch group during a latency period, when latching of data from both the first latch group and the second latch group has been completed, and outputting a detection signal.